1. Field of the Invention
The present invention relates to an insulated gate semiconductor device having a trench gate structure, and more particularly to a gate interconnection structure of the same device.
2. Description of the Background Art
An insulated gate semiconductor device having a trench gate structure is generally referred to as a vertical MOS transistor (as a UMOS from the shape of trenches). Since the vertical MOS transistor, having gate electrodes formed in a vertical direction unlike a lateral MOS transistor having planar gates, needs a smaller area for one cell, it allows an increase in the number of cells per unit area through micromachining. The increase in the number of cells per unit area (density) enlarges a channel area, allowing a larger amount of currents to flow in an ON state. The resistance of the UMOS transistor in this case is referred to as xe2x80x9cON-resistance (Ron)xe2x80x9d, which is a key item of characteristics of a device. Contrastively in the lateral MOS transistor, there is a limitation in reduction of ON-resistance Ron since increasing the cell density leads to an increase in j-FET resistance. For effective use of such a characteristic feature of the UMOS transistor, the gate trench structure is mainly adopted in power devices such as MOSFETs (MOS Field Effect Transistors) or IGBTs (Insulated Gate Bipolar Transistors).
Before pointing out problems to be solved in the present invention, first taken is an overview of a gate interconnection structure of a UMOSFET (no prior art) which is a unpublished product made by the present applicant company. In this unknown structure, a gate control electrode buried inside a trench which penetrates a p-type base layer is drawn up to above a surface of the trench at a cell end portion of the UMOSFET and the drawn-up portion of the gate control electrode is electrically connected to a gate electrode connected to a gate pad through a gate contact portion.
Next, discussion will be presented on a gate reliability test for the UMOSFET, relating to a main problem to be solved in the present invention. Further, a general HTGB test (high temperature gate bias test) will be herein discussed.
First, a UMOSFET is kept at a high temperature by using a constant temperature bath or a hot plate. In this state, a drain electrode and a source electrode are short-circuited by an external interconnection and a gate voltage VGS is applied across a gate electrode and the source electrode. At this time, tests are executed in both cases where the polarity of the gate voltage is positive and where it is negative. Further, with the gate voltage VGS set to a value close to a gate assured-proficiency voltage in a UMOSFET, the test is executed. Then, under this state, with the temperature of the UMOSFET kept constant, the gate voltage VGS is applied for a long time to check deterioration of a gate oxide film and the degree of variations in other characteristics.
In this case, at a corner portion of the trench, an electric field equivalent to the gate voltage VGS occurs against the gate oxide film formed on an inner wall of the trench, like in an ON-operation state. The electric field stress against the gate oxide film at the corner portion is much stronger than that in the ON-operation because of (1) high temperature atmosphere, (2) the value of the gate voltage VGS higher than that in the normal ON-operation and (3) a long-time continuous energization. Therefore, the HTGB test is means for acceleratedly checking the proficiency in withstand insulation voltage of the gate oxide film, and can be used for determinating an original lifetime of the gate oxide film.
In the product UMOSFET having the above gate interconnection structure, an electric field stress is applied to the whole surface of the gate oxide film through the HTGB test, and especially, a much stronger electric field stress is applied to the corner portion of the outermost trench. The reason are (1) that at the portion of the outermost trench, a silicon substrate is opened in a form almost square in order to draw the gate control electrode up to above the trench and the gate oxide film formed along a surface of the silicon substrate having a square bent portion has a film thickness much thinner at the square portion than that of other portions since the oxidation speed decreases at the square portion of the silicon substrate, and (2) that the withstand insulation voltage is lower at the portion of the outermost trench than a flat portion of the oxide film since the gate oxide film has a shape with a relatively large curvature at the portion of the outermost trench and much stronger electric field stress is applied to the gate oxide film at the portion of the outermost trench than that applied to other portions.
The following methods are possible to solve the above problem.
1) A method to make an oxide film at the corner portion thicker than those formed on the inner wall of the trench and the flat portion by implanting As (arsenic) as an n+-type impurity into the portion of the outermost trench, utilizing a phenomenon that the oxidation speed increases in a region in which n+-type impurities are implanted when a gate oxide film is formed by a heat treatment (no prior art).
2) A method to relieve the electric field stress by providing a round at the corner portion through an isotropic silicon etching which is performed immediately after the formation of the trench (no prior art).
3) A method to relieve the electric field stress by making the shape of the oxide film gentler through optimization of process conditions (heat history, gas atmosphere) in the formation of the gate oxide film (no prior art).
The method (1), however, produces an effect in a device which allows a long-time heat treatment, in other words, a device having a gate oxide film which is thick to some degree but can not produce a sufficient effect in a device which does not allow a long-time heat treatment, in other words, a device having a gate oxide film which is relatively thin.
Further, the method (2) raises a problem that the manufacturing process becomes complicate since an etching process is necessarily added. Moreover, in the method (2), the width of the trench becomes larger since the whole of trench is also etched at the same time, and this causes deterioration in yield because of short design margin and also causes a decrease in channel width in a transistor cell having a mesh structure, resulting in an increase in ON-resistance.
Furthermore, in the method (3), similarly in the method (2), since the gate oxide film has a round shape to some degree at the corner portion, it is possible to relieve the electric field stress to some degree but the withstand insulation voltage of the gate oxide film at the corner portion is nowhere near that of the gate oxide film at the flat portion because the film thickness of the gate oxide film at the corner portion does not become thicker. Therefore, the method (3) is not a radical solution.
It is a first object of the present invention to provide an insulated gate semiconductor device which ensures an improvement in yield through enhancing a withstand insulation voltage and reliability of gates.
It is a second object of the present invention to improve a main breakdown voltage between the first and second main electrodes in the insulated gate semiconductor device.
It is a third object of the present invention to reduce a gate wire resistance.
It is a fourth object of the present invention to reduce the number of process steps in a method of manufacturing such an insulated gate semiconductor device.
The present invention is intended for an insulated gate semiconductor device having an MOS transistor structure.
According to a first aspect of the present invention, the insulated gate semiconductor device having an MOS transistor structure includes a semiconductor substrate of a first conductivity type having a first main surface and a second main surface which are opposed to each other in a third direction, a base layer of a second conductivity type, a first trench, a first gate insulating film and a first main electrode. The base layer of a second conductivity type is formed from a cell region in the first main surface and a region in the first main surface which is defined by one end which is a boundary between the cell region and a terminal region adjacent to the cell region and the other end away from the boundary towards the terminal region by a first distance along a first direction, towards an inside of the semiconductor substrate along the third direction. The first trench is formed from the cell region in the first main surface, through the base layer, up to the inside of the semiconductor substrate along the third direction. The first gate insulating film is formed entirely on a bottom surface and side surfaces of the first trench. The first main electrode is formed on the second main surface. The first direction is parallel to the first main surface and orthogonal to the third direction, and a first depth from the first main surface to a bottom surface of the base layer is smaller than a second depth from the first main surface to the bottom surface of the first trench. The first trench has a plurality of first portions and a plurality of second portions, the plurality of first portions are arranged along a second direction orthogonal to the first direction and the third direction, each of the plurality of first portions has one end portion located on the boundary between the cell region and the terminal region and extends towards the one end portion along the first direction, and each of the plurality of second portions is located between adjacent first portions out of the plurality of first portions and extends along the second direction to connect the adjacent first portions to each other. The insulated gate semiconductor device further includes a plurality of second main electrode regions of the first conductivity type, a first gate control electrode, a second trench, a second gate insulating film, an insulating layer, a plurality of first contact portions, a plurality of second contact portions, a second main electrode, a third contact portion and a gate electrode. The plurality of second main electrode regions of the first conductivity type are each formed from a region in the cell region of the first main surface which is surrounded by the adjacent first portions and adjacent second portions out of the plurality of second portions corresponding to the adjacent first portions towards an inside of the base layer along upper portions of side surfaces of the adjacent first portions and upper portions of side surfaces of the adjacent second portions. The first gate control electrode is so formed inside the first trench as to be located beneath an upper surface of the first trench and fills the first trench with the first gate insulating film interposed therebetween. The second trench is formed from a region in the first main surface which is defined by one end which is the boundary and the other end away from the boundary toward the terminal region by a second distance shorter than the first distance along the first direction, through the base layer, up to the inside of the semiconductor substrate along the third direction, and has a third depth larger than the first depth and extends along the second direction, being connected to the one end portion which each of the plurality of first portions has. The second gate insulating film is formed entirely on a bottom surface and side surfaces of the second trench. The second gate control electrode is so formed inside the second trench as to be located beneath an upper surface of the second trench, fills the second trench with the second gate insulating film interposed therebetween, and is electrically connected to the first gate control electrode at the one end portion which each of the plurality of first portions has. The insulating layer is formed on an upper surface of the base layer, an upper surface of the first gate control electrode, an upper surface of the first gate insulating film, an upper surface of the second gate control electrode, an upper surface of the second gate insulating film and a region in the terminal region of the first main surface which is located outside an end of the base layer. The plurality of first contact portions are each so formed in the insulating layer as to expose part of an upper surface which each of the plurality of second main electrode regions has and an upper surface of a portion in the base layer which is surrounded by each of the plurality of second main electrode regions. The plurality of second contact portions are each so formed in the insulating layer as to expose part of an upper surface of a portion in the base layer which is surrounded by a side surface of the second trench on the side of the boundary, side surfaces of the adjacent first portions and a side surface of an outermost second portion of the plurality of second portions which faces the second trench. The second main electrode is formed in the plurality of first contact portions and the plurality of second contact portions and on a portion in the insulating layer which is located on the cell region of the first main surface, extends along the second direction, and is electrically connected to each of the plurality of second main electrode regions and the base layer. The third contact portion is so formed in the insulating layer as to expose part of the upper surface of the second gate control electrode. The gate electrode is formed inside the third contact portion, on a portion in the insulating layer which is defined by the boundary and a location away from the boundary towards the cell region along the first direction by a third distance not reaching an end portion of the second main electrode and on a portion in the insulating layer which is defined by the boundary and a location away from the boundary towards the terminal region along the first direction by a fourth distance longer than the first distance, extends along the second direction, and is electrically connected to the second gate control electrode through the third contact portion.
The first aspect of the present invention produces (1) an effect of preventing the electric field stress caused by application of the gate voltage from locally concentrating on the second gate insulating film, and further produces (2) an effect of ensuring improvement in main breakdown voltage between the first and second main electrodes by using the field plate effect.
According to a second aspect of the present invention, the insulated gate semiconductor device having an MOS transistor structure includes a semiconductor substrate of a first conductivity type having a first main surface and a second main surface which are opposed to each other in a third direction, a base layer of a second conductivity type, a first trench, a first gate insulating film and a first main electrode. The base layer of a second conductivity type is formed from a cell region in the first main surface and a region in the first main surface which is defined by one end which is a boundary between the cell region and a terminal region adjacent to the cell region and the other end away from the boundary towards the terminal region by a first distance along a first direction, towards an inside of the semiconductor substrate along the third direction. The first trench is formed from the cell region in the first main surface, through the base layer, up to the inside of the semiconductor substrate along the third direction. The first gate insulating film is formed entirely on a bottom surface and side surfaces of the first trench. The first main electrode is formed on the second main surface. The first direction is parallel to the first main surface and orthogonal to the third direction, and a first depth from the first main surface to a bottom surface of the base layer is smaller than a second depth from the first main surface to the bottom surface of the first trench. The first trench has a plurality of first portions and a plurality of second portions, the plurality of first portions are arranged along a second direction orthogonal to the first direction and the third direction, each of the plurality of first portions has one end portion located on the boundary between the cell region and the terminal region and extends towards the one end portion along the first direction, and each of the plurality of second portions is located between adjacent first portions out of the plurality of first portions and extends along the second direction to connect the adjacent first portions to each other. The insulated gate semiconductor device further includes a plurality of second main electrode regions of the first conductivity type, a first gate control electrode, a second trench, a second gate insulating film, a second gate control electrode, an insulating layer, a plurality of first contact portions, a plurality of second contact portions, a first electrode layer for second main electrode, a third contact portion, a gate electrode, a fourth contact portion and a second electrode layer for second main electrode. The plurality of second main electrode regions of the first conductivity type are each formed from a region in the cell region of the first main surface which is surrounded by the adjacent first portions and adjacent second portions out of the plurality of second portions corresponding to the adjacent first portions towards an inside of the base layer along upper portions of side surfaces of the adjacent first portions and upper portions of side surfaces of the adjacent second portions. The first gate control electrode is so formed inside the first trench as to be located beneath an upper surface of the first trench and fills the first trench with the first gate insulating film interposed therebetween. The second trench is formed from a region in the first main surface which is defined by one end which is the boundary and the other end away from the boundary towards the terminal region by a second distance shorter than the first distance along the first direction, through the base layer, up to the inside of the semiconductor substrate along the third direction, and has a third depth larger than the first depth and extends along the second direction, being connected to the one end portion which each of the plurality of first portions has. The second gate insulating film is formed entirely on a bottom surface and side surfaces of the second trench. The second gate control electrode is so formed inside the second trench as to be located beneath an upper surface of the second trench and fills the second trench with the second gate insulating film interposed therebetween, and is electrically connected to the first gate control electrode at the one end portion which each of the plurality of first portions has. The insulating layer is formed on an upper surface of the base layer, an upper surface of the first gate control electrode, an upper surface of the first gate insulating film, an upper surface of the second gate control electrode, an upper surface of the second gate insulating film and a region in the terminal region of the first main surface which is located outside an end of the base layer. The plurality of first contact portions are each so formed in the insulating layer as to expose part of an upper surface which each of the plurality of second main electrode regions has and an upper surface of a portion in the base layer which is surrounded by each of the plurality of second main electrode regions. The plurality of second contact portions are each so formed in the insulating layer as to expose part of an upper surface of a portion in the base layer which is surrounded by a side surface of the second trench on the side of the boundary, side surfaces of the adjacent first portions and a side surface of an outermost second portion of the plurality of second portions which faces the second trench. The first electrode layer for second main electrode is formed in the plurality of first contact portions and the plurality of second contact portions and on a portion in the insulating layer which is located on the cell region of the first main surface, having one end portion away from the boundary by a seventh distance along the first direction, extending along the second direction and being electrically connected to each of the plurality of second main electrode regions and the base layer. The third contact portion is so formed in the insulating layer as to expose part of the upper surface of the second gate control electrode. The gate electrode is formed inside the third contact portion, on a portion in the insulating layer which is defined by the boundary and a location away from the boundary towards the cell region along the first direction by a third distance shorter than the seventh distance and on a portion in the insulating layer which is defined by the boundary and a location away from the boundary towards the terminal region along the first direction by a fourth distance shorter than the first distance, extends along the second direction and is electrically connected to the second gate control electrode through the third contact portion. The fourth contact portion is so formed in the insulating layer as to expose part of an upper surface of a portion in the base layer which is sandwiched between a location away from the boundary towards the terminal region along the first direction by a fifth distance which is shorter than the first distance and longer than the fourth distance and the other end of the base layer away from the boundary by the first distance. The second electrode layer for second main electrode is formed in the fourth contact portion and on a portion in the insulating layer which is defined by the location away from the boundary towards the terminal region along the first direction by the fifth distance and a location away from the boundary towards the terminal region along the first direction by a sixth distance longer than the first distance, extending along the second direction and being electrically connected to the base layer through the fourth contact portion. Both the length of the first electrode layer for second main electrode and that of the second electrode layer for second main electrode along the second direction are longer than the length of the gate electrode along the second direction. The insulated gate semiconductor device further includes a connection layer. The connection layer having a side surface which is from one end portion of the gate electrode in the second direction by a predetermined distance along the second direction and extends along the first direction, is formed on a portion of the insulating layer which is defined by the one end portion of the first electrode layer for second main electrode and the location away from the boundary towards the terminal region by the fifth distance along the first direction, and configured to electrically connect the first electrode layer for second main electrode and the second electrode layer for second main electrode to each other.
The second aspect of the present invention produces the above effects (1) and (2).
According to a third aspect of the present invention, the insulated gate semiconductor device having an MOS transistor, structure includes a semiconductor substrate of a first conductivity type having a first main surface and a second main surface which are opposed to each other in a third direction, a base layer of a second conductivity type, a well layer of the second conductivity type, a first trench, a first gate insulating film and a first main electrode formed on the second main surface. The base layer of a second conductivity type is formed from a cell region in the first main surface towards a first bottom surface located inside the semiconductor substrate along the third direction, and has one end portion located on a boundary between the cell region and a terminal region adjacent to the cell region and a first depth from the first main surface to the first bottom surface. The well layer of the second conductivity type, being connected to the one end portion of the base layer in the boundary, is formed from a region in the terminal region of the first main surface which is defined by one end which is the boundary and the other end away from the boundary towards the terminal region by a first distance along the first direction, towards a fourth bottom surface located inside the semiconductor substrate along the third direction, and has a fourth depth from the first main surface to the fourth bottom surface. The first trench is formed from the cell region in the first main surface, through the base layer, up to a second bottom surface located inside the semiconductor substrate along the third direction, and has a second depth from the first main surface to the second bottom surface. The first gate insulating film is formed entirely on the second bottom surface and side surfaces of the first trench. The first direction is parallel to the first main surface and orthogonal to the third direction, the first depth is smaller than the second depth, the second depth is smaller than the fourth depth, and the well layer further has a base-layer covering portion formed from a portion in the first bottom surface of the base layer which is sandwiched between the boundary and a location away from the boundary by a fifth distance along the first direction, towards the fourth bottom surface of the well layer up to the inside of the semiconductor substrate. The first trench has a plurality of first portions and a plurality of second portions, the plurality of first portions are arranged along a second direction orthogonal to the first direction and the third direction, each of the plurality of first portions has one end portion located on the boundary between the cell region and the terminal region and extends towards the one end portion along the first direction, and each of the plurality of second portions is located between adjacent first portions out of the plurality of first portions and extends along the second direction to connect the adjacent first portions to each other. The insulated gate semiconductor device further includes a plurality of second main electrode regions of the first conductivity type, a first gate control electrode, a second trench, a second gate insulating film, a second gate control electrode, an insulating layer, a plurality of first contact portions, a plurality of second contact portions, a second main electrode, a third contact portion and a gate electrode. The plurality of second main electrode regions of the first conductivity type are each formed from a region in the cell region of the first main surface which is surrounded by the adjacent first portions and adjacent second portions out of the plurality of second portions corresponding to the adjacent first portions towards an inside of the base layer along upper portions of side surfaces of the adjacent first portions and upper portions of side surfaces of the adjacent second portions. The first gate control electrode is so formed inside the first trench as to be located beneath an upper surface of the first trench and fills the first trench with the first gate insulating film interposed therebetween. The second trench is formed from a region in the first main surface which is defined by the one end which is the boundary and the other end away from the boundary towards the terminal region by a second distance shorter than the first distance along the first direction, up to a third bottom surface located inside the well layer along the third direction, and has a third depth from the first main surface to the third bottom surface and extends along the second direction, being connected to the one end portion which each of the plurality of first portions has. The second gate insulating film is formed entirely on the third bottom surface and side surfaces of the second trench. The second gate control electrode is so formed inside the second trench as to be located beneath an upper surface of the second trench, fills the second trench with the second gate insulating film interposed therebetween, and is electrically connected to the first gate control electrode at the one end portion which each of the plurality of first portions has. The insulating layer is formed on an upper surface of the base layer, an upper surface of the first gate control electrode, an upper surface of the first gate insulating film, an upper surface of the second gate control electrode, an upper surface of the second gate insulating film, an upper surface of the well layer and a region in the terminal region of the first main surface, which is located outside an end of the well layer. The plurality of first contact portions are each so formed in the insulating layer as to expose part of an upper surface which each of the plurality of second main electrode regions has and an upper surface of a portion in the base layer which is surrounded by each of the plurality of second main electrode regions. The plurality of second contact portions are each so formed in the insulating layer as to expose part of an upper surface of a portion in the base layer which is surrounded by a side surface of the second trench on the side of the boundary, side surfaces of the adjacent first portions and a side surface of an outermost second portion of the plurality of second portions which faces the second trench. The second main electrode is formed in the plurality of first contact portions and the plurality of second contact portions and on a portion in the insulating layer which is located on the cell region of the first main surface, and has one end portion away from the boundary by a sixth distance larger than the fifth distance along the first direction and extends along the second direction, being electrically connected to each of the plurality of second main electrode regions and the base layer. The third contact portion is so formed in the insulating layer as to expose part of the upper surface of the second gate control electrode. The gate electrode is formed inside the third contact portion, on a portion in the insulating layer which is defined by the boundary and a location away from the boundary towards the cell region along the first direction by a third distance shorter than the fifth distance and on a portion in the insulating layer which is defined by the boundary and a location away from the boundary towards the terminal region along the first direction by a fourth distance longer than the first distance, extends along the second direction, and is electrically connected to the second gate control electrode through the third contact portion. The third depth is larger than the first depth, and the fourth depth is larger than the third depth.
The third aspect of the present invention produces the above effects (1) and (2), and further produces (3) an effect of relieving the electric field occurring at the tip portion of the second trench on application of the breakdown voltage between the first and second main electrodes and thereby stabilizing the breakdown voltage.
According to a fourth aspect of the present invention, the insulated gate semiconductor device having an MOS transistor structure includes a semiconductor substrate of a first conductivity type having a first main surface and a second main surface which are opposed to each other in a third direction, a base layer of a second conductivity type, a well layer of the second conductivity type, a first trench, a first gate insulating film and a first main electrode. The base layer of a second conductivity type is formed from a cell region in the first main surface towards a first bottom surface located inside the semiconductor substrate along the third direction, and has one end portion located on a boundary between the cell region and a terminal region adjacent to the cell region and a first depth from the first main surface to the first bottom surface. The well layer of the second conductivity type, being connected to the one end portion of the base layer in the boundary, is formed from a region in the terminal region of the first main surface which is defined by one end which is the boundary and the other end away from the boundary towards the terminal region by a first distance along the first direction, towards a fourth bottom surface located inside the semiconductor substrate along the third direction, and has a fourth depth from the first main surface to the fourth bottom surface. The first trench is formed from the cell region in the first main surface, through the base layer, up to a second bottom surface located inside the semiconductor substrate along the third direction, and has a second depth from the first main surface to the second bottom surface. The first gate insulating film is formed entirely on the second bottom surface and side surfaces of the first trench. The first main electrode is formed on the second main surface. The first direction is parallel to the first main surface and orthogonal to the third direction, the first depth is smaller than the second depth and the second depth is smaller than the fourth depth. The well layer further has a base-layer covering portion formed from a portion in the second bottom surface of the base layer which is sandwiched between the boundary and a location away from the boundary by an eighth distance along the first direction, towards the fourth bottom surface of the well layer up to an inside of the semiconductor substrate. The first trench has a plurality of first portions and a plurality of second portions, the plurality of first portions are arranged along a second direction orthogonal to the first direction and the third direction, each of the plurality of first portions has one end portion located on the boundary between the cell region and the terminal region and extends towards the one end portion along the first direction, and each of the plurality of second portions is located between adjacent first portions out of the plurality of first portions and extends along the second direction to connect the adjacent first portions to each other. The insulated gate semiconductor device further includes a plurality of second main electrode regions of the first conductivity type, a first gate control electrode, a second trench, a second gate insulating film, a second gate control electrode, an insulating layer, a plurality of first contact portions, a plurality of second contact portions, a first electrode layer for second main electrode, a third contact portion, a gate electrode, a fourth contact portion and a second electrode layer for second main electrode. The plurality of second main electrode regions of the first conductivity type are each formed from a region in the cell region of the first main surface, which is surrounded by the adjacent first portions and adjacent second portions out of the plurality of second portions corresponding to the adjacent first portions towards an inside of the base layer along upper portions of side surfaces of the adjacent first portions and upper portions of side surfaces of the adjacent second portions. The first gate control electrode is so formed inside the first trench as to be located beneath an upper surface of the first trench and fills the first trench with the first gate insulating film interposed therebetween. The second trench is formed from a region in the first main surface which is defined by the one end which is the boundary and the other end away from the boundary towards the terminal region by a second distance shorter than the first distance along the first direction, up to a third bottom surface located inside the well layer along the third direction, and has a third depth from the first main surface to the third bottom surface and extends along the second direction, being connected to the one end portion which each of the plurality of first portions has. The second gate insulating film is formed entirely on the third bottom surface and side surfaces of the second trench. The second gate control electrode is so formed inside the second trench as to be located beneath an upper surface of the second trench and fills the second trench with the second gate insulating film interposed therebetween, and is electrically connected to the first gate control electrode at the one end portion which each of the plurality of first portions has. The insulating layer is formed on an upper surface of the base layer, an upper surface of the first gate control electrode, an upper surface of the first gate insulating film, an upper surface of the second gate control electrode, an upper surface of the second gate insulating film, an upper surface of the well layer and a region in the terminal region of the first main surface which is located outside an end of the well layer. The plurality of first contact portions are each so formed in the insulating layer as to expose part of an upper surface which each of the plurality of second main electrode regions has and an upper surface of a portion in the base layer which is surrounded by each of the plurality of second main electrode regions. The plurality of second contact portions are each so formed in the insulating layer as to expose part of an upper surface of a portion in the base layer which is surrounded by a side surface of the second trench on the side of the boundary, side surfaces of the adjacent first portions and a side surface of an outermost second portion of the plurality of second portions which faces the second trench. The first electrode layer for second main electrode is formed in the plurality of first contact portions and the plurality of second contact portions and on a portion in the insulating layer which is located on the cell region of the first main surface, and has one end portion away from the boundary by a seventh distance longer than the eighth distance along the first direction and extends along the second direction, being electrically connected to each of the plurality of second main electrode regions and the base layer. The third contact portion is so formed in the insulating layer as to expose part of the upper surface of the second gate control electrode. The gate electrode is formed inside the third contact portion, on a portion in the insulating layer which is defined by the boundary and a location away from the boundary towards the cell region along the first direction by a third distance shorter than the eighth distance and on a portion in the insulating layer which is defined by the boundary and a location away from the boundary towards the terminal region along the first direction by a fourth distance shorter than the first distance, extends along the second direction, and is electrically connected to the second gate control electrode through the third contact portion. The fourth contact portion is so formed in the insulating layer as to expose part of an upper surface of a portion in the well layer which is sandwiched between a location away from the boundary towards the terminal region along the first direction by a fifth distance which is shorter than the first distance and longer than the fourth distance and the other end of the well layer away from the boundary by the first distance. The second electrode layer for second main electrode is formed in the fourth contact portion and on a portion in the insulating layer which is defined by the location away from the boundary towards the terminal region along the first direction by the fifth distance and a location away from the boundary towards the terminal region along the first direction by a sixth distance longer than the first distance, extending along the second direction and being electrically connected to the well layer through the fourth contact portion. Both the length of the first electrode layer for second main electrode and that of the second electrode layer for second main electrode along the second direction are longer than the length of the gate electrode along the second direction. The insulated gate semiconductor device further includes a connection layer. The connection layer having a side surface which is away from one end portion of the gate electrode in the second direction by a predetermined distance along the second direction and extends along the first direction, is formed on a portion of the insulating layer which is defined by the one end portion of the first electrode layer for second main electrode and the location away from the boundary towards the terminal region by the fifth distance along the first direction, and configured to electrically connect the first electrode layer for second main electrode and the second electrode layer for second main electrode to each other. The third depth is larger than the first depth, and the fourth depth is larger than the third depth.
The fourth aspect of the present invention produces the above effects (1), (2) and (3).
According to a fifth aspect of the present invention, the insulated gate semiconductor device having an MOS transistor structure includes a semiconductor substrate of a first conductivity type having a first main surface and a second main surface which are opposed to each other in a third direction, a base layer of a second conductivity type, a first trench, a first gate insulating film and a first main electrode formed on the second main surface. The base layer of a second conductivity type is formed from a cell region in the first main surface towards a first bottom surface located inside the semiconductor substrate along the third direction, and has one end portion located on a boundary between the cell region and a terminal region adjacent to the cell region and a first depth from the first main surface to the first bottom surface. The first trench is formed from the cell region in the first main surface, through the base layer, up to a second bottom surface located inside the semiconductor substrate along the third direction, and has a second depth from the first main surface to the second bottom surface. The first gate insulating film is formed entirely on the second bottom surface and side surfaces of the first trench. The first direction is parallel to the first main surface and orthogonal to the third direction, and the first depth is smaller than the second depth. The first trench has a plurality of first portions and a plurality of second portions, the plurality of first portions are arranged along a second direction orthogonal to the first direction and the third direction, each of the plurality of first portions has one end portion located on the boundary between the cell region and the terminal region and extends towards the one end portion along the first direction, and each of the plurality of second portions is located between adjacent first portions out of the plurality of first portions and extends along the second direction to connect the adjacent first portions to each other. The insulated gate semiconductor device further includes a plurality of second main electrode regions of the first conductivity type, a first gate control electrode, a second trench, a second gate insulating film, a second gate control electrode, an insulating layer, a plurality of first contact portions, a plurality of second contact portions, a second main electrode, a third contact portion and a gate electrode. The plurality of second main electrode regions of the first conductivity type are each formed from a region in the cell region of the first main surface, which is surrounded by the adjacent first portions and adjacent second portions out of the plurality of second portions corresponding to the adjacent first portions, towards an inside of the base layer along upper portions of side surfaces of the adjacent first portions and upper portions of side surfaces of the adjacent second portions. The first gate control electrode is so formed inside the first trench as to be located beneath an upper surface of the first trench and fills the first trench with the first gate insulating film interposed therebetween. The second trench is formed from a region in the first main surface which is defined by the one end which is the boundary and the other end away from the boundary toward the terminal region by a first distance along the first direction, up to a third bottom surface located inside the semiconductor substrate along the third direction, and has a third depth from the first main surface to the third bottom surface and extends along the second direction, being connected to the one end portion which each of the plurality of first portions has. The second gate insulating film is formed entirely on the third bottom surface and side surfaces of the second trench. The second gate control electrode is so formed inside the second trench as to be located beneath an upper surface of the second trench and fills the second trench with the second gate insulating film interposed therebetween, and is electrically connected to the first gate control electrode at the one end portion which each of the plurality of first portions has. The insulating layer is formed on an upper surface of the base layer, an upper surface of the first gate control electrode, an upper surface of the first gate insulating film, an upper surface of the second gate control electrode, an upper surface of the second gate insulating film and a portion of the first main surface which is located outside one of the side surfaces of the second trench on the side of the terminal region. The plurality of first contact portions are each so formed in the insulating layer as to expose part of an upper surface which each of the plurality of second main electrode regions has and an upper surface of a portion in the base layer which is surrounded by each of the plurality of second main electrode regions. The plurality of second contact portions are each so formed in the insulating layer as to expose part of an upper surface of a portion in the base layer which is surrounded by a side surface of the second trench on the side of the boundary, side surfaces of the adjacent first portions and a side surface of an outermost second portion of the plurality of second portions which faces the second trench. The second main electrode is formed in the plurality of first contact portions and the plurality of second contact portions and on a portion in the insulating layer which is located on the cell region of the first main surface, has one end portion away from the boundary by a fourth distance along the first direction and extends along the second direction, and is electrically connected to each of the plurality of second main electrode regions and the base layer. The third contact portion is so formed in the insulating layer as to expose part of the upper surface of the second gate control electrode. The gate electrode is formed inside the third contact portion, on a portion in the insulating layer which is defined by the boundary and a location away from the boundary towards the cell region along the first direction by a third distance shorter than the fourth distance and on a portion in the insulating layer which is defined by the boundary and a location away from the boundary towards the terminal region along the first direction by a second distance longer than the first distance, extends along the second direction, and is electrically connected to the second gate control electrode through the third contact portion. The third depth is larger than the first depth. No semiconductor layer of the second conductivity type is formed in a portion of the semiconductor substrate which is located immediately below the gate electrode, which is defied by a side surface of the second trench on the side of the terminal region and the location away from the boundary towards the terminal region by the second distance along the first direction.
The fifth aspect of the present invention produces the above effects (1) and (2) and further produces (4) an effect of avoiding deterioration in main breakdown voltage due to the curvature of the base layer located outside the second trench and thereby ensuring further improvement in main breakdown voltage.
According to a sixth aspect of the present invention, the insulated gate semiconductor device having an MOS transistor structure includes a semiconductor substrate of a first conductivity type having a first main surface and a second main surface which are opposed to each other in a third direction, a base layer of a second conductivity type, a trench, a gate insulating film and a first main electrode. The base layer of a second conductivity type is formed from a cell region in the first main surface and a region in the first main surface which is defined by one end which is a boundary between the cell region and a terminal region adjacent to the cell region and the other end away from the boundary towards the terminal region by a first distance along a first direction, towards an inside of the semiconductor substrate along the third direction. The trench is formed from the cell region in the first main surface, through the base layer, up to the inside of the semiconductor substrate along the third direction. The gate insulating film is formed entirely on a bottom surface and side surfaces of the trench. The first main electrode is formed on the second main surface. The first direction is parallel to the first main surface and orthogonal to the third direction, and a first depth from the first main surface to a bottom surface of the base layer is smaller than a second depth from the first main surface to the bottom surface of the trench. The trench has a plurality of first portions and a plurality of second portions, the plurality of first portions are arranged along a second direction orthogonal to the first direction and the third direction, each of the plurality of first portions has one end portion located on the boundary between the cell region and the terminal region and extends towards the one end portion along the first direction, and each of the plurality of second portions is located between adjacent first portions out of the plurality of first portions and extends along the second direction to connect the adjacent first portions to each other. The insulated gate semiconductor device further includes a plurality of second main electrode regions of the first conductivity type, a gate control electrode, an insulating layer, a plurality of first contact portions, a plurality of second contact portions, a second main electrode, a plurality of third contact portions and a gate electrode. The plurality of second main electrode regions of the first conductivity type are each formed from a region in the cell region of the first main surface which is surrounded by the adjacent first portions and adjacent second portions out of the plurality of second portions corresponding to the adjacent first portions towards an inside of the base layer along upper portions of side surfaces of the adjacent first portions and upper portions of side surfaces of the adjacent second portions. The gate control electrode is so formed inside the trench as to be located beneath an upper surface of the trench and fills the trench with the gate insulating film interposed therebetween. The insulating layer is formed on an upper surface of the base layer, an upper surface of the gate control electrode, an upper surface of the gate insulating film and a region in the terminal region of the first main surface which is located outside an end of the base layer. The plurality of first contact portions are each so formed in the insulating layer as to expose part of an upper surface which each of the plurality of second main electrode regions has and an upper surface of a portion in the base layer which is surrounded by each of the plurality of second main electrode regions. The plurality of second contact portions are each so formed in the insulating layer as to expose part of an upper surface of a portion in the base layer which is defined by the boundary, side surfaces of the adjacent first portions and a side surface of an outermost second portion of the plurality of second portions which faces the boundary. The second main electrode is formed in the plurality of first contact portions and the plurality of second contact portions and on a portion in the insulating layer which is located on the cell region of the first main surface, extends along the second direction, and is electrically connected to each of the plurality of second main electrode regions and the base layer. The plurality of third contact portions which are provided for the plurality of first portions, respectively, are each so formed in the insulating layer as to expose a portion which is sandwiched between a first location away from the boundary along the first direction by a fourth distance and a second location away from the boundary along the first direction by a fifth distance longer than the fourth distance in an upper surface of a portion of the gate control electrode filling each of the plurality of first portions. The gate electrode is formed inside each of the plurality of third contact portions, on a portion in the insulating layer which is defined by the boundary and a location away from the boundary towards the cell region along the first direction by a third distance longer than the fifth distance and on a portion in the insulating layer which is defined by the boundary and a location away from the boundary towards the terminal region along the first direction by a second distance longer than the first distance, extends along the second direction, and is electrically connected to the gate control electrode through the plurality of third contact portions.
The sixth aspect of the present invention produces the above effects (1) and (2) and further produces (5) an effect of eliminating the xcexc loading effect in trench etching because of no second trench and thereby uniformizing the depths of trenches.
The present invention is also intended for a method of manufacturing a gate interconnection structure.
According to a seventh aspect of the present invention, the method of manufacturing a gate interconnection structure includes the following steps (a) to (g). The step (a) is to form a base layer of a second conductivity type from a main surface of a semiconductor substrate of a first conductivity type up to an inside of the semiconductor substrate along a third direction. The step (b) is to form a first trench penetrating the base layer, extending along a first direction which is in parallel with the main surface and orthogonal to the third direction and having a bottom surface inside the semiconductor substrate and a second trench penetrating the base layer, extending along a second direction orthogonal to the first direction and the third direction while being connected to one end portion of the first trench in the first direction and having a bottom surface inside the semiconductor substrate. The step (c) is to form a first gate oxide film on the bottom surface and side surfaces of the first trench and a second gate oxide film on the bottom surface and side surfaces of the second trench. The step (d) is to form a first gate control electrode which fills the first trench with the first gate oxide film interposed therebetween and a second gate control electrode which fills the second trench with the second gate oxide film interposed therebetween. The step (e) is to form an insulating layer, which covers an upper surface of the first gate control electrode and an upper surface of the second gate control electrode, on the main surface of the semiconductor substrate. The step (f) is to form a gate contact portion in the insulating layer, the gate contact portion exposing the upper surface of the second gate control electrode. The step (g) is to form a gate electrode on an upper surface of the insulating layer, the gate electrode filling the gate contact portion and having one end portion protruding outside beyond an end portion of the base layer in the first direction.
The seventh aspect of the present invention produces an effect of reducing the number of process steps as compared with the method of manufacturing the unpublished product made by the present applicant company in which the gate control electrode is drawn up to above the trench at the corner portion of the trench.
According to an eighth aspect of the present invention, the method of manufacturing a gate interconnection structure includes the following steps (a) to (g). The step (a) is to form a base layer of a second conductivity type from a main surface of a semiconductor substrate of a first conductivity type up to an inside of the semiconductor substrate along a third direction. The step (b) is to form a first trench penetrating the base layer, extending along a first direction which is in parallel with the main surface and orthogonal to the third direction and having a bottom surface inside the semiconductor substrate and a second trench penetrating the base layer, extending along a second direction orthogonal to the first direction and the third direction while being connected to one end portion of the first trench in the first direction and having a bottom surface inside the semiconductor substrate. The step (c) is to form a first gate oxide film on the bottom surface and side surfaces of the first trench and a second gate oxide film on the bottom surface and side surfaces of the second trench. The step (d) is to form a first gate control electrode which fills the first trench with the first gate oxide film interposed therebetween and a second gate control electrode which fills the second trench with the second gate oxide film interposed therebetween. The step (e) is to form an insulating layer, which covers an upper surface of the first gate control electrode and an upper surface of the second gate control electrode, on the main surface of the semiconductor substrate. The step (f) is to form a gate contact portion and a source contact portion in the insulating layer, the gate contact portion exposing the upper surface of the second gate control electrode, the source contact portion exposing an upper surface of the base layer located outside the second trench. The step (g) is to form a gate electrode and a source electrode on an upper surface of the insulating layer, the gate electrode filling the gate contact portion, the source electrode filling the source contact portion and having one end portion protruding outside beyond an end portion of the base layer in the first direction.
The eighth aspect of the present invention produces an effect of easily manufacturing a gate interconnection structure in which the source electrode itself serves as a field plate.